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| SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset March 2001 Revised July 2002 SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset General Description The SSTV16859 is a dual output 13-bit register designed for use with 184 and 232 pin DDR-1 memory modules. The device has a differential input clock, SSTL-2 compatible data inputs and a LVCMOS compatible RESET input. The device has been designed to meet the JEDEC DDR module register specifications. The device has been fabricated on an advanced submicron CMOS process and is designed to operate at power supplies of less than 3.6V's. Features I Compliant with DDR-I registered module specifications I Operates at 2.5V 0.2V VDD I SSTL-2 compatible input structure I SSTL-2 compliant output structure I Differential SSTL-2 compatible clock inputs I Low power mode when device is reset I Industry standard 64 pin TSSOP package I Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Ordering Code: Order Number SSTV16859G (Note 1)(Note 2) SSTV16859MTD (Note 2) Package Number BGA96A MTD64 Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: Ordering code "G" indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. (c) 2002 Fairchild Semiconductor Corporation DS500414 www.fairchildsemi.com SSTV16859 Connection Diagrams Pin Assignment for TSSOP Pin Descriptions Pin Name Q1A-Q13A Q1B-Q13B D1-D13 RESET CK CK VREF VDDQ VDD NC SSTL-2 Compatible Register Inputs Asynchronous LVCMOS Reset Input Positive Master Clock Input Negative Master Clock Input Voltage Reference Pin for SSTL level inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs Electrically Isolated No Connect Description SSTL-2 Compatible Register Outputs FBGA Pin Assignments 1 A B C D E F G H J K L M N Pin Assignment for FBGA P R T NC Q12A Q10A Q8A Q6A Q4A Q2A Q1A Q12B Q10B Q8B Q6B Q4B Q2B NC NC 2 NC Q13A Q11A Q9A Q7A Q5A Q3A Q13B Q11B Q9B Q7B Q5B Q3B Q1B NC NC 3 NC GND GND VDDQ VDDQ VDDQ GND GND GND VDDQ VDDQ VDDQ GND GND NC NC 4 NC GND GND VDDQ VDD VDD GND GND VREF VDD VDD VDDQ GND GND NC NC 5 NC NC NC D13 D11 D9 D7 NC NC NC D5 D3 D1 NC NC NC 6 NC NC NC D12 D10 D8 RESET CK CK NC D6 D4 D2 NC NC NC Truth Table RESET L H H H H Dn X or Floating L H X X CK X or Floating CK X or Floating Qn L L H Qn-1 Qn-1 L H H L L = Logic LOW H = Logic HIGH X = Don't Care but not floating unless noted = LOW-to-HIGH Clock Transition = HIGH-to-LOW Clock Transition Qn-1 = Output Remains in Previously Clocked State (Top Thru View) www.fairchildsemi.com 2 SSTV16859 Functional Description The SSTV16859 is a 13-bit dual register with SSTL-2 compatible inputs and outputs. Input data is transferred to output data on the rising edge of the differential clock pair. When the RESET signal is asserted LOW all outputs are placed into the LOW logic state and all input comparators are disabled for power savings. Output glitches are prevented by disabling the internal registers more quickly than the input comparators. When RESET is removed, the system designer must insure the clock and data inputs to the device are stable during the rising transition of the RESET signal. The SSTL-2 data inputs transition based on the value of VREF. VREF is a stable system reference used for setting the trip point of the input buffers of the SSTV16859 and other SSTL-2 compatible devices. The RESET signal is a standard CMOS compatible input and is not referenced to the VREF signal. Logic Diagram For n = 1 to 13 3 www.fairchildsemi.com SSTV16859 Absolute Maximum Ratings(Note 3) Supply Voltage (VDDQ) Supply Voltage (VDD) Reference Voltage (VREF ) Input Voltage (VI) Output Voltage (VO) Outputs Active (Note 4) DC Input Diode Current (IIK) VI < 0V VI > VDD DC Output Diode Current (IOK) VO < 0V VO > VDDQ DC Output Source/Sink Current (IOH/IOL) DC VDD or Ground Current per Supply Pin (IDD or Ground) Storage Temperature Range (Tstg) ESD (Human Body Model) -0.5V to +3.6V -0.5V to +3.6V -0.5V to +3.6V -0.5V to VDD +0.5V -0.5V to VDDQ + 0.5V -50 mA +50 mA -50 mA +50 mA 50 mA 100 mA -65C to +150C 7000V Recommended Operating Conditions (Note 5) Power Supply (VDDQ) Power Supply (VDD) Operating Range Reference Supply (VREF = VDDQ/2) Termination Voltage (VTT) Input Voltage Output Voltage (VO) Output in Active States Output Current IOH/IOL VDD = 2.3V to 2.7V Free Air Operating Temperature (TA) 0V to VDDQ 1.15 to 1.35 VREF 40 mV 0 to VDD VDDQ to 2.7V 2.3V to 2.7V 20 mA 0C to +70C Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is asserted LOW. DC Electrical Characteristics (2.3V VDD 2.7V) Symbol VIKL VIKH VIH-AC VIL-AC VIH-DC VIL-DC VIH VIL VICR VI(PP) VOH VOL II IDD Parameter Input LOW Clamp Voltage Input HIGH Clamp Voltage AC HIGH Level Input Voltage AC LOW Level Input Voltage DC HIGH Level Input Voltage DC LOW Level Input Voltage HIGH Level Input Voltage LOW Level Input Voltage Conditions II = -18 mA II = +18 mA Data Inputs Data Inputs Data Inputs Data Inputs RESET RESET 0.97 360 2.3 to 2.7 2.3 2.3 to 2.7 2.3 2.7 VDD - 0.2 1.95 0.2 0.35 5.0 10 2.7 25 mA 1.7 0.7 1.53 VREF+150mV VREF-150mV VDD (V) 2.3 2.3 VREF+310mV VREF-310mV Min Typ Max -1.2 3.5 Units V V V V V V V V V mV V V A A Common Mode Input Voltage Range CK, CK Peak to Peak Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Static Standby Static Operating CK, CK IOH = -100 A IOH = -16 mA IOL = 100 A IOL = 16 mA VI = VDD or GND RESET = GND, IO = 0 RESET = VDD, IO = 0 VI = VIH(AC) or VIL(AC) RESET = VDD, IO = 0 VI = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Dynamic Operating Current per Data Input RESET = VDD, IO = 0 VI = VIH(AC) or VIL(AC) CK, CK Duty Cycle 50% Data Input = 1/2 Clock Rate 50% Duty Cycle 2.7 IDDD Dynamic Operating Current Clock Only 120 A/MHz 15 A/MHz www.fairchildsemi.com 4 SSTV16859 DC Electrical Characteristics Symbol ROH ROL RO Parameter Output HIGH On Resistance Output LOW On Resistance | ROH - ROL | (Continued) VDD (V) 2.3 to 2.7 2.3 to 2.7 2.5 Conditions IOH = -20 mA IOL = 20 mA IO = 20 mA, TA = 25C Min 7 7 Typ Max 20 20 4 Units AC Electrical Characteristics (Note 6) TA = 0C to +70C, CL = 30 pF, RL = 50 Symbol Parameter VDD = 2.5V 0.2V; VDDQ = 2.5V 0.2V Min fMAX tW tACT (Note 7) tINACT (Note 7) tS tH tREM tPHL, tPLH tPHL Maximum Clock Frequency Pulse Duration, CK, CK HIGH or LOW (Figure 2) Differential Inputs Activation Time, data inputs must be LOW after RESET HIGH (Figure 3) Differential Inputs De-activation Time, data and clock inputs must be held at valid levels (not floating) after RESET LOW Setup Time, Fast Slew Rate (Note 8)(Note 9) (Figure 5) Setup Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5) Hold Time, Fast Slew Rate (Note 8)(Note 10) (Figure 5) Hold Time, Slow Slew Rate (Note 9)(Note 10) (Figure 5) Reset Removal Time (Figure 7) Propagation Delay CK, CK to Qn (Figure 4) Propagation Delay RESET to Qn (Figure 6) 0.75 0.9 0.75 0.9 10 1.1 2.8 5.0 ns ns ns ns ns 22 ns 200 2.5 22 Typ Max MHz ns ns Units Note 6: Refer to Figure 1 through Figure 7. Note 7: This parameter is not production tested. Note 8: For data signal input slew rate 1 V/ns. Note 9: For data signal input slew rate 0.5 V/ns and < 1 V/ns. Note 10: For CK, CK signals input slew rates are 1 V/ns. Capacitance (Note 11) Symbol CIN Parameter Data Pin Input Capacitance CK, CK - Input Capacitance RESET Min 2.2 2.2 2.3 Typ Max 3.2 3.2 3.3 Units pF pF pF Conditions VDD = 2.5V, VI = VREF 310 mV VDD = 2.5V, VICR = 1.25, VI(PP) = 360 mV VDD = 2.5V, VI = VDD or GND Note 11: TA = +25C, f = 1 MHz, Capacitance is characterized but not tested. 5 www.fairchildsemi.com SSTV16859 AC Loading and Waveforms (See Notes A through F below) Note: CL includes probe and jog capacitance FIGURE 1. AC Test Circuit FIGURE 2. Voltage Waveforms - Pulse Duration Note: IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. FIGURE 3. Voltage and Current Waveforms Inputs Active and Inactive Times FIGURE 4. Voltage Waveforms Propagation Delay Times FIGURE 5. Voltage Waveforms - Setup and Hold Times FIGURE 6. Voltage Waveforms RESET Propagation Delay Times Note A: All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z0 = 50, input slew rate = 1V/ns 20% (unless otherwise specified). Note B: The outputs are measured one at a time with one transition per measurement. Note C: VTT = VREF = VDD/2. Note D: VIH = VREF +310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. Note E: VIL = VREF -310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. Note F: Removal time (tREM) is tested with one data input held active HIGH. The propagation time from CK to the corresponding output must meet valid timing specifications for the measurement to be accurate. FIGURE 7. Voltage Waveforms RESET Removal Delay Times www.fairchildsemi.com 6 SSTV16859 Physical Dimensions inches (millimeters) unless otherwise noted 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A 7 www.fairchildsemi.com SSTV16859 Dual Output 13-Bit Register with SSTL-2 Compatible I/O and Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 64-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD64 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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